The present invention relates to the field of power converters, and in particular to a hysteretic converter arranged to rapidly compensate for a load step.
Various schemes of controlling a DC to DC power converter are known. In a linear controlled power converter, one of the output voltage and output current are sensed and fedback to the controller via an error amplifier. A reference value, reflective of a target output, is further received by the error amplifier, and differences in output from the target output are detected and compensated for, typically by adjusting the amount of time that an electronically controlled switch is closed. In such an embodiment, the output voltage or current varies about the target output, and the average output over time may equal the target output. Such a linear regulation control however is inappropriate when a quick reaction to large changes in load is required.
In order to overcome this difficulty, a hysteretic converter is utilized. The hysteretic converter comprises at least one electronically controlled switch, a comparator and an inductor, the electronically controlled switch being closed responsive to the output of the comparator. The comparator is arranged to close the electronically controlled switch promptly responsive to the instantaneous output voltage falling below a first reference signal, thus driving the output voltage higher without the delay of an integrator or other low bandwidth circuitry. Various schemes for opening the electronically controlled switch exist, including, but not limited to, comparing the output voltage to a second reference and defining a predetermined fixed on time for the electronically controlled switch.
FIG. 1 illustrates a high level schematic diagram of a hysteretic converter 10 of the prior art comprising: a hysteretic comparator 20 illustrated as a Schmidt trigger comparator; a switched mode power supply 40, illustrated without limitation as a buck converter constituted of a first electronically controlled switch 50 illustrated without limitation as a p-channel field-effect transistor (PFET), a second electronically controlled switch 60 illustrated without limitation as an n-channel field-effect transistor (NFET), an inductor 70 and an output capacitor 80; a voltage divider 90; a reference voltage circuitry 100, comprising a ramp current source 110, a resistor 120 and a capacitor 130. Additionally, a load 140 is further illustrated. An input voltage VIN is coupled to the source of PFET 50, and the drain of PFET 50 is coupled to a first end of inductor 70 and to the drain of NFET 60. A second end of inductor 70 is coupled to a first end of output capacitor 80 and to a first end of load 140, the voltage thereat denoted output voltage VOUT. A second end of load 140, a second end of output capacitor 80 and the source of NFET 60 are coupled to a common potential.
A predetermined portion of output voltage VOUT is further coupled to the non-inverting input of hysteretic comparator 20, via voltage divider 90, denoted feedback signal FB. The inverting input of hysteretic comparator 20 is coupled to a first end of each of capacitor 130, resistor 120 and ramp current source 110. A second end of each of ramp current source 110, resistor 120 and capacitor 130 is coupled to the common potential. The output of hysteretic comparator 20 is coupled to both the gate of PFET 50 and to the gate of NFET 60. Optionally, (not shown) a gate driving circuit is provided between the output of hysteretic comparator 20 and the gates of PFET 50 and NFET 60.
In operation, ramp current source 110 is arranged to generate a ramped current, which is converted to a reference voltage VREF by resistor 120 and capacitor 130. When feedback signal FB falls to less than the threshold value signal fed to the inverting input of hysteretic comparator 20, i.e. reference voltage VREF, hysteretic comparator 20 enables current flow through PFET 50, thus connecting inductor 70 to input voltage VIN and enabling current flow through inductor 70, defined as positive when flowing in the direction of output capacitor 80 and increasing over time thus increasing output voltage VOUT. When feedback signal FB is greater than reference voltage VREF, hysteretic comparator 20 enables current flow through NFET 60, thus connecting inductor 70 to the common potential and current flow through inductor 70 decreases over time thus decreasing output voltage VOUT. Hysteresis is provided by hysteretic comparator 20 to avoid instability.
The response of hysteretic converter 10 is quite fast. Unfortunately, during load step conditions at load 140 undershoot and overshoot can become very high, which is undesirable.